Keysight N4903A Serial BERT
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Keysight N4903A J-BERT is a high-performance serial bit error rate tester with integrated jitter injection and calibrated stress testing capabilities for receivers up to 12.5 Gb/s.
Product details
| Model | N4903A |
| Manufacturer | Keysight |
| Category | Bit Error Rate Testing |
| Availability | Made to order |
Description
Overview
The Keysight N4903A is a high-performance serial bit error rate tester (BERT) that provides a complete jitter tolerance test solution for characterization of serial gigabit devices. The J-BERT platform features complete, integrated, and calibrated jitter composition for stressed eye testing of receivers up to 12.5 Gb/s. It is the ideal choice for R&D and validation teams who need to characterize and stress chips and transceiver modules with serial I/O ports.
Key Features
- Pattern generator and error detector from 150 Mb/s to 7 Gb/s or 12.5 Gb/s options
- Greater than 0.5 UI calibrated and integrated jitter injection
- Excellent signal performance and sensitivity
- Built-in clock data recovery with tunable and compliant loop bandwidth
- Analysis of undeterministic traffic and complex pattern sequences
- Subrate clock outputs for economical receiver testing
- Support for clockless and differential interfaces
- Expandable architecture with configurable options for future needs
Applications
- Automated and compliant jitter tolerance testing per industry standards
- PCIe, SATA, FB-DIMM, Fibre Channel, and Gigabit Ethernet testing
- XFP/XFI and CEI (Common Electrical Interface) standard validation
- Serial interface stress testing and receiver characterization
- Chip and module validation with serial I/O up to 12.5 Gb/s
Specifications
| Data Rate Range | 150 Mb/s to 12.5 Gb/s |
| Jitter Injection | >0.5 UI, calibrated and integrated |
| Pattern Generator Output Options | 150 Mb/s to 7 Gb/s or 12.5 Gb/s |
| Clock Data Recovery | Built-in with tunable and compliant loop bandwidth |
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Keysight N4903A Serial BERT
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