Keysight N4880A Reference Clock Multiplier
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Keysight N4880A Reference Clock Multiplier locks pattern generators to system reference clocks for accurate receiver testing of PCIe, MIPI M-PHY, and SD UHS-II devices.
Product details
| Model | N4880A |
| Manufacturer | Keysight |
| Category | Bit Error Rate Testing |
| Availability | Made to order |
Description
Overview
The N4880A is a multiplying phase-locked loop (PLL) that extends the capabilities of Keysight's J-BERT and ParBERT pattern generators by enabling them to lock to system reference clocks. This functionality is essential for accurate receiver testing of devices in PCIe, MIPI M-PHY, and SD UHS-II standards where the device under test derives its sampling clock from the same reference clock. The N4880A supports 2 or 5 MHz loop bandwidth options and tolerates significant spread spectrum clocking variations.
Key Features
- Supports 19.2 MHz, 26 to 52 MHz, and 100 MHz reference clock multiplication
- 2 or 5 MHz loop bandwidth options for different application requirements
- Transparent to 33 kHz spread spectrum clocking on reference clock
- Input sensitivity of 100 mVpp differential for small signal handling
- USB connection with standalone graphical user interface
- Enables jitter tolerance testing aligned with device under test clocking
Applications
- PCI Express 1.0, 2.0, 3.0 receiver testing and validation
- MIPI M-PHY gear 1-3 characterization
- SD card UHS-II host device testing
- Stressed-pattern generator synchronization with system reference clocks
- Accurate jitter tolerance testing under reproducible conditions
Specifications
| Accurate and Simplified Receiver Testing for PCI Express, MIPI M-PHY and SD UHS-II | The N4880A reference clock multiplier fills a critical requirement for R&D and test engineers who need to characterize and release the next generation of PCI Express main boards, MIPI M-PHY chipsets and SD card UHS-II host devices. With its support for multiple reference-clock rates, the N4880A will help you accurately characterize and verify standards compliance under easy-to-reproduce test conditions. |
| Lock the Stressed-Pattern Generator to a System Reference Clock | In common reference-clock architectures, where the host cannot be driven by an external reference clock it’s necessary to lock the stressed-pattern generator to the same system reference clock used by the receiver under test. This is because the receiver under test also derives its sampling clock from this reference clock. Locking the stressed pattern generator to the same reference clock as the receiver under test ensures accurate and reproducible jitter-tolerance test results. |
| Get the most Precise and Reproducible Receiver Tolerance Test Results for PCI Express Mainboards, MIPI M-PHY and SD UHS-II Hosts | The N4880A provides a multiplying phase-locked loop (PLL) which enables users to lock the pattern generator of J-BERT N4903B or ParBERT 81250A to a system reference clock. Spread Spectrum Clocking (SSC) and low frequency jitter are fed through the N4880A up to its PLL loop bandwidth of 2 or 5 MHz. The N4880A tolerates huge amounts of SSC for UHS-II reference clocks and offers excellent input sensitivity to handle very low voltage levels. |
| Features | Parameters |
| Power Consumption | 100–240 V, ~50/60 Hz, 80 VA max |
| Operating Temperature | 5 to 40°C (–23 to 104°F) |
| Storage Temperature | –40 to 70° C |
| Operating humidity | 95% relative humidity non-condensing |
| Storage Humidity | 50% relative humidity |
| Rack Mount without Bumper | 1/2 x 19” width, 1U height |
| Weight Net | 1.9 kg (4.2 lb) |
| Weight Shipping | ~4.5 kg (10 lb) |
| N4880A | Reference clock multiplier Included accessories: One 50 Ω termination, 3.5 mm; USB cable; CD-ROM with software and user documentation; Functional Test Report; ROHS addendum |
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Keysight N4880A Reference Clock Multiplier
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